FIG. 1 is a block diagram showing a high-speed digital computer bus system 20. The bus system includes a number of discrete devices 22–24, which communicate over an electrical bus 25 at very high speeds. The bus includes a plurality of data transmission lines.
This system includes a master device 22 and a plurality of slave devices 23–24. The master device 22 initiates and controls data exchanges over bus 25. During a data exchange, any one of devices 22–24 can act as either a transmitting component or a receiving component. Generally, there is only one transmitting component during any single data exchange. However, there can be one or a plurality of receiving components during a data exchange.
FIG. 2 illustrates the configuration and operation of a single bus line 26 between a transmitting component 27 and a receiving component 28. The bus line is terminated at one end to a termination voltage Vterm through a termination impedance Rterm. Transmitting component 27 has a line current driver 29, which produces line voltages with specified relationships to a reference voltage VREF.
More specifically, driver 29 is a current source or sink that creates desired voltage drops across termination impedance Rterm. The current driver 29 is turned on or otherwise enabled to produce one logic level voltage, and is turned off or otherwise disabled to produce another logic level voltage. In actual embodiment, the current driver 29 sinks current when enabled, and does not sink or source current when disabled. When disabled, the line voltage is approximately equal to Vterm. When enabled, the line voltage is lower than Vterm, because of a voltage drop through termination impedance Rterm.
As an example, suppose that Vterm is 2.5 volts. When driver 29 is disabled there is no current through the bus line, and the bus line voltage is equal to Vterm, or 2.5 volts. This is the high logic level, and is referred to as VOH. On the other hand, when driver 29 is enabled the current through the bus line drops the line voltage to a lower value VOL, which in this example is 1.9 volts. VOL is the low logic level.
The voltage difference between VOH and VOL, also referred to as a line voltage swing Vswing, is controlled by the value of termination resistance Vterm and the amount of line current IO (which is controlled by the current driver 29). It is desirable to limit the line voltage swing as much as possible to enable higher bus speeds. If the voltage swing is too small, however, a receiving component will not be able to reliably distinguish between high and low logic level voltages.
FIG. 2 also illustrates how the line voltage is interpreted at receiving component or device 28. Specifically, the received line voltage VO is compared to reference voltage VREF by a comparator 40. If VO is greater than VREF, the line voltage represents a high logic level. If VO is less than VREF, the line voltage represents a low logic level.
For this determination to be valid, the transmitting component needs to set its VOH and VOL relative to VREF. Preferably, VOH and VOL are established symmetrically around VREF. In the example of FIG. 3, VOH is 2.5 volts, VREF is 2.2 volts, and VOL is 1.9 volts. This yields a 0.6 volt voltage swing: 0.3 volts on either side of VREF.
FIG. 3 shows a circuit for creating a symmetrical voltage swing around VREF during a calibration process. This circuit, which is used only during the calibration, utilizes two different bus lines 60 and 61, each of which are similar to the bus line 26 shown in FIG. 2.
The calibration circuit has current drivers 62 and 63, and a current control 64 which in this case is an up/down counter. Current drivers 62 and 63 are switched on and off by data control lines (not shown) to create high and low voltage levels VOH and VOL on the corresponding bus lines. When a driver is on, the magnitude of its output current is determined by the value contained in up/down counter 64.
Bus lines 60 and 61 extend to receiving components and a termination resistor (not shown). Within the transmitting component, however, the high and low output voltages VOH and VOL are sampled for purposes of adjusting the current driver outputs to create a symmetric voltage swing. Specifically, a simple R over R resistive voltage divider 66 is placed between a line producing a high logic voltage VOH and another line producing a low logic level VOL. In this case, it is assumed that line 60 is at the high voltage level, with current driver 62 inactive; and bus line 61 is at the low voltage level, with current driver 63 being active. Furthermore, the resistive divider 66 is configured to produce an intermediate output voltage VI that is equal to (VOH+VOL)/2. For symmetry around VREF, VI should be equal to VREF. A feedback system is used to minimize the voltage difference between VI and VREF. Both VI and VREF are connected to the inputs of a comparator 68, which produces a logic voltage VF that is high when VI−VREF>0, and low when VI VREF<0. VF is then connected to counter 64. The output of the counter, in turn, is connected to control the output of current drivers 62 and 63.
The circuit works as follows. During calibration, counter 64 is enabled and/or clocked, and repetitively adjusts its output either up or down depending on the logic value of VF. This increases or decreases the output of current driver 63. The output current is thus adjusted until the value of counter 64 has settled. At this point, VI−VREF=zero-meaning that VI=VREF and that VOH and VOL are symmetric around VREF. At this point, the value of counter 64 is frozen until the next calibration (although minor adjustments might be made by temperature control circuits).
In most cases, this calibration is performed at system initialization. Optionally, the calibrated current control value (from the counter) can be stored in a current control register and used during normal bus operation to control the magnitude of IO. This value can then be subject to temperature correction circuits to determine the current control value at any given time. Alternatively, the calibration can be performed periodically to account for temperature and voltage variations.
Ideally, both the transmitting component and a receiving component have the same value of VREF. In practice, however, this can be difficult to achieve due to signal line losses and/or noise. Accordingly, VREF at the receiving component is often somewhat different than VREF at the transmitting component. Furthermore, VOH and VOL often change as they propagate through the signal line, again due to losses and noise. Thus, the relationship between VOH, VOL and VREF may not be the same at the transmitting component as it is at the receiving component. In other words, Vswing might not be symmetric around VREF by the time the signals reach a receiving component.
In the bus configuration described above, line losses generally affect VOL more than VOH. At VOL, the voltage is being produced by a current through the bus line, so the voltage can be affected along the length of the bus line by resistive and capacitive loads. At VOH, however, there is no line current, and therefore less opportunity for the voltage to be affected along the length of the bus line. This situation affects both the line voltage swing and the relationship of VOL with VREF.
The non-symmetry at the receiving component has negative effects. If VOL is higher at the receiving component, the voltage margin from VREF to VOL is decreased. When VOL is lower at the receiving component, low-side margin is increased, but the higher Vswing would cause more reflections, which could degrade the high-side margin during a subsequent data transfer cycle. This issue has been addressed by introducing a degree of asymmetry at the transmitting component in order to provide symmetry at the receiving component: the current drivers at the transmitting component are adjusted to achieve voltage symmetry at the receiving component. The amount of asymmetry at the transmitting component is referred to as the overdrive factor (ODF).
A desired asymmetry at the transmitting component can be created by varying the ratio of voltage divider 66. Thus, instead of producing a signal VI that is 50% of the way from VOL to VOH, the resistors can be chosen to implement any other percentage. This creates asymmetry at the transmitting component to correct for any asymmetry that would otherwise be present at the receiving component.
In actual embodiment, the ratio of voltage divider 66 has been controlled by a symmetry control register. Different values can be loaded into the symmetry control register to create different degrees of asymmetry at the transmitting component. Symmetry control values can be stored for a plurality of different receivers, and used when transmitting to those receivers. This accounts for variations in conditions at different receivers.
In some such circuits, the value of counter 64 is stored after completion of the calibration process, and loaded into a current control register during actual operation. A plurality of values can be stored, corresponding to different receiving components. The current control register is reloaded for communication with different receiving components.
The desired line current and corresponding divider percentage or ratio are determined during system design—prior to manufacture of the transmitting component or prior to manufacture of a circuit that utilizes the transmitting component. The determination is based on testing and/or simulating, and choosing voltage divider ratios that are predicted to work with the different receivers in light of the actual circuit layout. In some cases, the transmitting component includes logic for predicting required asymmetry values based on known system parameters such as distances between components.
The inventors, however, have discovered and developed a way to dynamically determine appropriate line drive currents at system initialization, based on tested characteristics of the circuits themselves.